Research Interests



Research Projects


Below are links to current and recently funded projects associated with my research. Click on these links to obtain a short description and links to papers associated with an individual project.

NSF Sphinx: Combining Data and Instruction Level Parallelism through Demand Execution of Imperative Programs
NSF grant CCF-1533846
NSF Supporting FSU Student Research with CTH Faculty on Efficient and Secure Mobile Systems
NSF grant IIA-1358147
NSF Static Pipelining, an Approach for Ultra-Low Power Embedded Processors
NSF grant CNS-0964413
NSF Reducing Virus Propagation in Mobile Devices
NSF grant CNS-0915926
NSF Enhancing the Effectiveness of Utilizing an Instruction Register File
NSF grant CNS-0615085
NSF SPARTA: Static Parametric Timing Analysis to Support Dynamic Decisions in Embedded Systems
NSF grant CCR-0312493
NSF Branch Elimination by Condition Merging
NSF grant CCR-0208892
NSF A Comprehensive, Retargetable Embedded Systems Software Development Environment
NSF grant EIA-0072043
NSF Automatic Validation of Code-Improving Transformations and Related Applications
NSF grant CCR-9904943
NSF Experimental Evaluation of Scalable Optimization Techniques
NSF grant EIA-9806525
ONR Predicting Execution Time of Large Code Segments
ONR grant N00014-94-1-0006


Journal Publications

  1. "Quick Compilers Using Peephole Optimizations" by J. W. Davidson and D. B. Whalley in Software Practice & Experience, January 1989, pages 195-203.

  2. "Methods for Saving and Restoring Register Values across Function Calls" by J. W. Davidson and D. B. Whalley in Software Practice & Experience, February 1991, pages 149-165.

  3. "A Design Environment for Addressing Architecture and Compiler Interactions" by J. W. Davidson and D. B. Whalley in Microprocessors and Microsystems, November 1991, pages 459-472.

  4. "Relating Static and Dynamic Machine Code Measurements" by J. W. Davidson, J. R. Rabung, and D. B. Whalley in IEEE Transactions on Computers, April 1992, pages 444-454.

  5. "A Design Environment for Addressing Architecture and Compiler Interactions" by J. W. Davidson and D. B. Whalley in Information and Software Technology, November 1992, pages 707-720. (This is a reprint of the Microprocessors and Microsystems paper.)

  6. "Techniques for Fast Instruction Cache Performance Evaluation" by D. B. Whalley in Software Practice & Experience, January 1993, pages 95-118.

  7. "A Retargetable Technique for Predicting Execution Time of Code Segments" by M. G. Harmon, T. P. Baker, and D. B. Whalley in Real-Time Systems, September 1994, pages 159-182.

  8. "Automatic Isolation of Compiler Errors" by D. B. Whalley in ACM Transactions on Programming Languages and Systems, September 1994, pages 1648-1659.

  9. "Fast Context Switches: Compiler and Architectural Support for Preemptive Scheduling" by J. S. Snyder, D. B. Whalley, and T. P. Baker in Microprocessors and Microsystems, February 1995, pages 35-42.

  10. "Graphical Visualization of Compiler Optimizations" by M. R. Boyd and D. B. Whalley in Journal of Programming Languages, June 1995, pages 69-94.

  11. "Bounding Pipeline and Instruction Cache Performance" by C. A. Healy, R. D. Arnold, F. Mueller, D. B. Whalley, and M. G. Harmon in IEEE Transactions on Computers, January 1999, pages 53-70.

  12. "Timing Constraint Specification and Analysis" by L. Ko, N. Al-Yaqoubi, C. Healy, E. Ratliff, R. Arnold, D. Whalley, and M. Harmon in Software Practice & Experience, January 1999, pages 77-98.

  13. "Timing Analysis for Data Caches and Wrap-Around Fill Caches" by R. White, F. Mueller, C. Healy, D. Whalley, and M. Harmon, in Real-Time Systems, November 1999, pages 209-233.

  14. "Effectively Exploiting Indirect Jumps" by G. Uh and D. Whalley, in Software Practice & Experience, December 1999, pages 1061-1101.

  15. "Supporting Timing Analysis by Automatic Bounding of Loop Iterations" by C. Healy, M. Sjodin, V. Rustagi, D. Whalley, and R. van Engelen, in Real-Time Systems, May 2000, pages 121-148.

  16. "Improving Memory Hierarchy Performance for Irregular Applications Using Data and Computation Reorderings" by J. Mellor-Crummey, D. Whalley, and K. Kennedy in the International Journal on Parallel Processing, vol 29, no 3, June 2001, pages 217-247.

  17. "Automatic Detection and Exploitation of Branch Constraints for Timing Analysis" by C. Healy and D. Whalley, in IEEE Transactions on Software Engineering, August 2002, pages 763-781.

  18. "Efficient and Effective Branch Reordering Using Profile Data" by M. Yang, G. Uh, and D. Whalley, in ACM Transactions on Programming Languages and Systems, vol 24, no 6, November 2002, pages 667-697.

  19. "Fast Memory Bank Assignment for Fixed-point Digital Signal Processors" by J. Cho, Y. Paek, and D. Whalley, in ACM Transactions on Design Automation of Electronic Systems, vol 9, no 1, January 2004, pages 52-74.

  20. "Automatic Validation of Code-Improving Transformations on Low-Level Program Representations" by R. van Engelen, D. Whalley, and X. Yuan, in Science of Computer Programming, August 2004, vol 52, pages 257-280.

  21. "Branch Elimination by Condition Merging" by W. Kreahling, D. Whalley, M. Bailey, X. Yuan, G. Uh, and R. van Engelen, in Software Practice & Experience, January 2005, pages 51-74.

  22. "Compiler Transformations for Effectively Exploiting a Zero Overhead Loop Buffer" by G. Uh, Y. Wang, D. Whalley, S. Jinturkar, V. Cao, C. Burns, Y. Paek, in Software Practice & Experience, April 2005, pages 393-412.

  23. "Fast and Efficient Searches for Effective Optimization Phase Sequences" by P. Kulkarni, S. Hines, D. Whalley, J. Hiser, J. Davidson, D. Jones, in ACM Transactions on Architecture and Code Optimization, June 2005, pages 165-198.

  24. "Improving WCET by Applying a WC Code Positioning Optimization" by W. Zhao, D. Whalley, C. Healy, F. Mueller, in ACM Transactions on Architecture and Code Optimization, December 2005, pages 335-365.

  25. "Improving WCET by Applying Worst-Case Path Optimizations" by W. Zhao, W. Kreahling, D. Whalley, C. Healy, F. Mueller in Real-Time Systems, October 2006, pages 129-152.

  26. "VISTA: VPO Interactive System for Tuning Applications" by P. Kulkarni, W. Zhao, S. Hines, D. Whalley, X. Yuan, R. van Engelen, K. Gallivan, J. Hiser, J. Davidson, B. Cai, M. Bailey, H. Moon, K. Cho, Y. Paek, D. Jones, in ACM Transactions on Embedded Computing Systems, November 2006, pages 819-863.

  27. "The Worst-Case Execution Time Problem - Overview of Methods and Survey of Tools" by R. Wilhelm, J. Engblom, A. Ermedahl, N. Holsti, S. Thesing, D. Whalley, G. Bernat, C. Ferdinand, R. Heckman, T. Mitra, F. Mueller, I. Puaut, P. Puschner, J. Staschulat, P. Stenstrom in ACM Transactions on Embedded Computing Systems, vol 7, no 3, April 2008, 53 pages.

  28. "Practical Exhaustive Optimization Phase Order Exploration and Evaluation" by P. Kulkarni, D. Whalley, G. Tyson, J. Davidson in ACM Transactions on Architecture and Code Optimization, vol 6, no 1, March 2009, pages 1-36.

  29. "Parametric Timing Analysis and Its Application to Dynamic Voltage Scaling" by S. Mohan, F. Mueller, W. Hawkins, M. Root, C. Healy, D. Whalley, E. Vivancos in ACM Transactions on Embedded Computing Systems, vol 10, no 2, December 2010, 34 pages.

  30. "Program Differentiation" by D. Chang, S. Hines, P. West, G. Tyson, and D. Whalley in the Journal of Circuits, Systems, and Computers, vol 21, no 2, April 2012, 22 pages.

  31. "An Overview of Static Pipelining" by I. Finlayson, G. Uh, D. Whalley, and G. Tyson in IEEE Computer Architecture Letters (CAL), vol 11, no 1, June 2012, pages 17-20.

  32. "Designing a Practical Data Filter Cache to Improve Both Energy Efficiency and Performance" by A. Bardizbanyan, M. Sjalander, D. Whalley, and P. Larsson-Edefors in ACM Transactions on Architecture and Code Optimization, vol 10, no 4, December 2013.

  33. "Reducing Instruction Fetch Energy in Multi-Issue Processors" by P. Gavin, D. Whalley, and M. Sjalander in ACM Transactions on Architecture and Code Optimization, vol 10, no 4, December 2013.

Conference Publications

  1. "Ease: An Environment for Architecture Study and Experimentation" by J. W. Davidson and D. B. Whalley in the Proceedings of the ACM SIGMETRICS '90 Conference on Measurement and Modeling of Computer Systems, May 1990, pages 259-260.

  2. "Reducing the Cost of Branches by Using Registers" by J. W. Davidson and D. B. Whalley in the Proceedings of the 17th Annual IEEE/ACM International Symposium on Computer Architecture, May 1990, pages 182-191.

  3. "Fast Instruction Cache Performance Evaluation Using Compile-Time Analysis" by D. B. Whalley in the Proceedings of the ACM SIGMETRICS and PERFORMANCE '92 Conference on Measurement and Modeling of Computer Systems, June 1992, pages 13-22. [ vertical slides, horizontal slides]

  4. "Avoiding Unconditional Jumps by Code Replication" by F. Mueller and D. B. Whalley in the Proceedings of the ACM SIGPLAN '92 Conference on Programming Language Design and Implementation, June 1992, pages 322-330. [ vertical slides, horizontal slides]

  5. "A Retargetable Technique for Predicting Execution Time" by M. G. Harmon, T. P. Baker, and D. B. Whalley in the Proceedings of the IEEE Real-Time Systems Symposium, December 1992, pages 68-77.

  6. "Isolation and Analysis of Optimization Errors" by M. R. Boyd and D. B. Whalley in the Proceedings of the ACM SIGPLAN '93 Conference on Programming Language Design and Implementation, June 1993, pages 26-35. [ slides]

  7. "Efficient On-the-fly Analysis of Program Behavior and Static Cache Simulation" by F. Mueller and D. B. Whalley in the Proceedings of the First International Static Analysis Symposium, September 1994, pages 101-115. [ slides]

  8. "Bounding Worst-Case Instruction Cache Performance" by R. D. Arnold, F. Mueller, D. B. Whalley, and M. G. Harmon in the Proceedings of the IEEE Real-Time Systems Symposium, December 1994, pages 172-181. [ vertical slides, horizontal slides]

  9. "Fast Instruction Cache Analysis via Static Cache Simulation" by F. Mueller and D. B. Whalley in the Proceedings of the IEEE Annual Simulation Symposium, April 1995, pages 105-114. [ slides]

  10. "Avoiding Conditional Branches by Code Replication" by F. Mueller and D. B. Whalley in the Proceedings of the ACM SIGPLAN '95 Conference on Programming Language Design and Implementation, June 1995, pages 56-66. [ vertical slides, horizontal slides]

  11. "Integrating the Timing Analysis of Pipelining and Instruction Caching" by C. A. Healy, D. B. Whalley, and M. G. Harmon in the Proceedings of the IEEE Real-Time Systems Symposium, December 1995, pages 288-297. [ vertical slides, horizontal slides]

  12. "Supporting the Specification and Analysis of Timing Constraints" by L. Ko, C. Healy, E. Ratliff, R. Arnold, D. Whalley, and M. G. Harmon in the Proceedings of the IEEE Real-Time Technology and Applications Symposium, June 1996, pages 170-178. [ vertical slides, horizontal slides]

  13. "Timing Analysis for Data Caches and Set-Associative Caches" by R. White, F. Mueller, C. Healy, D. Whalley, and M. G. Harmon in the Proceedings of the IEEE Real-Time Technology and Applications Symposium, June 1997, pages 192-202. [ vertical slides, horizontal slides]

  14. "Coalescing Conditional Branches into Efficient Indirect Jumps" by G. Uh and D. Whalley in the Proceedings of the Static Analysis Symposium, September 1997, pages 315-329. [ vertical slides, horizontal slides]

  15. "Decreasing Process Memory Requirements by Overlapping Program Portions" by R. L. Bowman, E. J. Ratliff, and D. B. Whalley in the Proceedings of the IEEE Hawaii International Conference on System Sciences, January 1998, vol 7, pages 115-124. [ vertical slides, horizontal slides]

  16. "Bounding Loop Iterations for Timing Analysis" by C. Healy, M. Sjodin, V. Rustagi, and D. Whalley in the Proceedings of the IEEE Real-Time Technology and Applications Symposium, June 1998, pages 12-21. [ vertical slides, horizontal slides]

  17. "Improving Performance by Branch Reordering" by M. Yang, G. Uh, and D. Whalley in the Proceedings of the ACM SIGPLAN '98 Conference on Programming Language Design and Implementation, June 1998, pages 130-141. [slides]

  18. "Tighter Timing Predictions by Automatic Detection and Exploitation of Value-Dependent Constraints" by C. Healy and D. Whalley in the Proceedings of the IEEE Real-Time Technology and Applications Symposium, June 1999, pages 79-88. [ vertical slides, horizontal slides]

  19. "Improving Memory Hierarchy Performance for Irregular Applications" by J. Mellor-Crummey, D. Whalley, and K. Kennedy in the Proceedings of the ACM International Conference on Supercomputing, June 1999, pages 425-433. [ slides]

  20. "Techniques for Effectively Exploiting a Zero Overhead Loop Buffer" by G. Uh, Y. Wang, D. Whalley, S. Jinturkar, C. Burns, V. Cao in the Proceedings of the International Conference on Compiler Construction, March 2000, pages 157-172. [ vertical slides, horizontal slides]

  21. "On Providing Useful Information for Analyzing and Tuning Applications" by J. Mellor-Crummey, R. Fowler, D. Whalley in the Proceedings of the ACM SIGMETRICS/Performance Joint International Conference on Measurement and Modeling of Computer Systems, June 2001, pages 332-333. [ slides]

  22. "Tools for Application-Oriented Performance Tuning" by J. Mellor-Crummey, R. Fowler, D. Whalley in the Proceedings of the ACM International Conference on Supercomputing, June 2001, pages 154-165.

  23. "Using a Swap Instruction to Coalesce Loads and Stores" by A. Qasem, D. Whalley, X. Yuan, and R. van Engelen in the Proceedings of the European Conference on Parallel Computing, August 2001, pages 235-240.

  24. "Register and Memory Assignment for Non-orthogonal Architectures via Graph Coloring and MST Algorithms" by J. Cho, Y. Paek, D. Whalley in the ACM Conference on Languages, Compilers, and Tools for Embedded Systems, June 2002, pages 130-138.

  25. "VISTA: A System for Interactive Code Improvement" by W. Zhao, B. Cai, D. Whalley, M. Bailey, R. van Engelen, X. Yuan, J. Hiser, J. Davidson, K. Gallivan, and D. Jones in the Proceedings of the ACM SIGPLAN Conference on Language, Compilers, and Tools for Embedded Systems, June 2002, pages 155-164. [ slides]

  26. "Validation of Code-Improving Transformations for Embedded Systems" by R. van Engelen, D. Whalley, and X. Yuan, in the Proceedings of the ACM SIGAPP Symposium on Applied Computing, March 2003, pages 684-691.

  27. "Finding Effective Optimization Phase Sequences" by P. Kulkarni, W. Zhao, H. Moon, K. Cho, D. Whalley, J. Davidson, M. Bailey, Y. Paek, K. Gallivan, D. Jones in the Proceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems, June 2003, pages 12-23. [ slides]

  28. "Branch Elimination via Multi-Variable Condition Merging" by W. Kreahling, D. Whalley, M. Bailey, X. Yuan, G. Uh, R. van Engelen in the Proceedings of the European Conference on Parallel and Distributed Computing, August 2003, pages 261-270. [ slides]

  29. "Tuning the WCET of Embedded Applications" by W. Zhao, P. Kulkarni, D. Whalley, C. Healy, F. Mueller, G. Uh in the Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, May 2004, pages 472-481. [ slides]

  30. "Fast Searches for Effective Optimization Phase Sequences" by P. Kulkarni, S. Hines, J. Hiser, D. Whalley, J. Davidson, D. Jones in the Proceedings of the ACM SIGPLAN Conference on Programming Language Design & Implementation, June 2004, pages 171-182. [ slides]

  31. "WCET Code Positioning" by W. Zhao, D. Whalley, C. Healy, F. Mueller in the Proceedings of the IEEE Real-Time Systems Symposium, December 2004, pages 81-91. [ slides]

  32. "Improving WCET by Optimizing Worst-Case Paths" by W. Zhao, W. Kreahling, D. Whalley, C. Healy, F. Mueller in the Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, March 2005, pages 138-147. [ slides]

  33. "Timing Analysis for Sensor Network Nodes of the Atmega Processor Family" by S. Mohan, F. Mueller, D. Whalley, C. Healy in the Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, March 2005, pages 405-414.

  34. "Improving Program Efficiency by Packing Instructions into Registers" by S. Hines, J. Green, G. Tyson, D. Whalley in the Proceedings of the IEEE/ACM International Symposium on Computer Architecture, June 2005, pages 260-271. [ slides]

  35. "Tuning High Performance Kernels through Empirical Compilation" by R. Whaley, D. Whalley in the Proceedings of the International Conference on Parallel Processing, June 2005, pages 89-98. [ slides]

  36. "Using De-optimization to Re-optimize Code" by S. Hines, P. Kulkarni, D. Whalley, J. Davidson in the Proceedings of the ACM EMSOFT Conference, September 2005, pages 114-123. [ slides]

  37. "Improving the Energy and Execution Efficiency of a Small Instruction Cache by Using an Instruction Register File" by S. Hines, G. Tyson, D. Whalley, in the Proceedings of the Watson Conference on Interaction between Architecture, Circuits, and Compilers, September 2005, pages 160-169. [ slides]

  38. "Reducing Instruction Fetch Cost by Packing Instructions into Register Windows" by S. Hines, G. Tyson, D. Whalley, in the Proceedings of the IEEE/ACM International Symposium on Microarchitecture, November 2005, pages 19-29. [ slides]

  39. "ParaScale: Exploiting Parametric Timing Analysis for Real-Time Schedulers and Dynamic Voltage Scaling" by S. Mohan, F. Mueller, W. Hawkins, M. Root, C. Healy, D. Whalley, in the Proceedings of the IEEE Real-Time Systems Symposium, December 2005, pages 233-242.

  40. "Exhaustive Optimization Phase Order Search Exploration" by P. Kulkarni, D. Whalley, G. Tyson, J. Davidson in the Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, March 2006, pages 306-318. [ slides]

  41. "On the Use of Compilers in DSP Laboratory Instruction" by M. Kleffner, D. Jones, J. Hiser, P. Kulkarni, J. Parent, S. Hines, D. Whalley, J. Davidson, K. Gallivan in the Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing, May 2006, pages 977-980.

  42. "Reducing the Cost of Conditional Transfers of Control by Using Comparison Specifications" by W. Kreahling, S. Hines, D. Whalley, G. Tyson in the Proceedings of the ACM Conference on Languages, Compilers, and Tools for Embedded Systems, June 2006, pages 64-71. [ slides]

  43. "In Search of Near-Optimal Optimization Phase Orderings" by P. Kulkarni, D. Whalley, G. Tyson, J. Davidson in the Proceedings of the ACM Conference on Languages, Compilers, and Tools for Embedded Systems, June 2006, pages 83-92. [ slides]

  44. "Adapting Compilation Techniques to Enhance the Packing of Instructions into Registers" by S. Hines, D. Whalley, G. Tyson in the Proceedings of the IEEE/ACM International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, October 2006, pages 43-53. [ slides]

  45. "Fast, Accurate Design Space Exploration of Embedded Systems Memory Configurations" by J. Hiser, J. Davidson, D. Whalley in the Proceedings of the ACM Symposium on Applied Computing, March 2007.

  46. "Evaluating Heuristic Optimization Phase Order Search Algorithms" by P. Kulkarni, D. Whalley, G. Tyson, J. Davidson in the Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, March 2007, pages 157-169. [ slides]

  47. "Addressing Instruction Fetch Bottlenecks by Using an Instruction Register File" by S. Hines, G. Tyson, D. Whalley in the Proceedings of the ACM Conference on Languages, Compilers, and Tools for Embedded Systems, June 2007, pages 165-174. [ slides]

  48. "Generalizing Parametric Timing Analysis" by J. Coffman, C. Healy, F. Mueller, D. Whalley in the Proceedings of the ACM Conference on Languages, Compilers, and Tools for Embedded Systems, June 2007, pages 152-154.

  49. "Facilitating Compiler Optimizations through the Dynamic Mapping of Alternate Register Structures" by C. Zimmer, S. Hines, P. Kulkarni, G. Tyson, D. Whalley in the Proceedings of the IEEE/ACM International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, October 2007, pages 165-169. [ slides]

  50. "Guaranteeing Hits to Improve the Efficiency of a Small Instruction Cache" by S. Hines, D. Whalley, G. Tyson in the Proceedings of the IEEE/ACM International Symposium on Microarchitecture December 2007, pages 433-444.

  51. "Guaranteeing Instruction Fetch Behavior with a Lookahead Instruction Fetch Engine" by S. Hines, Y. Peress, P. Gavin, D. Whalley, G. Tyson in the Proceedings of the ACM Conference on Languages, Compilers, and Tools for Embedded Systems, June 2009, pages 119-128.

  52. "Improving Both the Performance Benefits and Speed of Optimization Phase Sequence Searches" by P. Kulkarni, M. Jantz, D. Whalley in the Proceedings of the ACM Conference on Languages, Compilers, and Tools for Embedded Systems, April 2010, pages 95-104. [ slides]

  53. "Improving Data Access Efficiency by Using a Tagless Access Buffer (TAB)" by A. Bardizbanyan, P. Gavin, D. Whalley, M. Sjalander, P. Larsson-Edefors, S. McKee, P. Stenstrom in the Proceedings of the ACM/IEEE International Symposium on Code Generation and Optimization, February 2013, pages 269-279.

  54. "Improving Processor Efficiency by Statically Pipelining Instructions" by I. Finlayson, B. Davis, P. Gavin, G. Uh, D. Whalley, M. Sjalander, G. Tyson in the Proceedings of the ACM Conference on Languages, Compilers, and Tools for Embedded Systems, June 2013, pages 33-43.

  55. "Speculative Tag Access for Reduced Energy Dissipation in Set-Associative L1 Data Caches" by A. Bardizbanyan, M. Sjalander, D. Whalley, P. Larsson-Edefors in the Proceedings of the IEEE International Conference on Computer Design, October 2013, pages 302-308.

  56. "A Journey toward Obtaining Our First NSF S-STEM (Scholarship) Grant" by A. Wang, G. Tyson, D. Whalley, R. van Engelen, Z. Zhang in the Proceedings of the ACM SIGCSE Technical Symposium, March 2014.

  57. "Reducing Set-Associative L1 Data Cache Energy by Early Load Data Dependence Detection (ELD3)" by A. Bardizbanyan, M. Sjalander, D. Whalley, P. Larsson-Edefors in the Proceedings of the IEEE/ACM Design Automation and Test in Europe Conference, March 2014.

  58. "Optimizing Transfers of Control in the Static Pipeline Architecture" by R. Baird, P. Gavin, M. Sjalander, D. Whalley, G. Uh in the Proceedings of the ACM Conference on Languages, Compilers, and Tools for Embedded Systems, June 2015.

  59. "Improving Data Access Efficiency by Using Context-Aware Loads and Stores" by A. Bardizbanyan, M. Sjalander, D. Whalley, P. Larsson-Edefors in the Proceedings of the ACM Conference on Languages, Compilers, and Tools for Embedded Systems, June 2015. [ slides]

  60. "Scheduling Instruction Effects for a Statically Pipelined Processor" by B. Davis, P. Gavin, R. Baird, M. Sjalander, I. Finlayson, F. Rasapour, G. Cook, G. Uh, D. Whalley, G. Tyson in the Proceedings of the IEEE/ACM International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, October 2015.

  61. "Practical Way Halting by Speculatively Accessing Halt Tags" by D. Moreau, A. Bardizbanyan, M. Sjalander, D. Whalley, P. Larsson-Edefors in the Proceedings of the IEEE/ACM Design Automation and Test in Europe Conference, March 2016.

  62. "Remix: On-demand Live Randomization" by Y. Chen, Z. Wang, D. Whalley, L. Lu in the Proceedings of the ACM Conference on Data and Application Security and Privacy, March 2016.

  63. "Redesigning a Tagless Access Buffer That Requires Minimal ISA Changes" by C. Sanchez, P. Gavin, D. Moreau, M. Sjalander, D. Whalley, P. Larsson-Edefors, S. McKee in the Proceedings of the IEEE/ACM International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, October 2016.

Workshop Publications

  1. "Predicting Instruction Cache Behavior" by F. Mueller, D. B. Whalley, M. G. Harmon in the Proceedings of the ACM SIGPLAN Workshop on Language, Compiler, and Tool Support for Real-Time Systems, June 1994. [ slides]

  2. "On Debugging Real-Time Applications" by F. Mueller and D. B. Whalley in the Proceedings of the ACM SIGPLAN Workshop on Language, Compiler, and Tool Support for Real-Time Systems, June 1994. [ slides]

  3. "Real-Time Debugging by Minimal Hardware Simulation" by F. Mueller, D. B. Whalley, and M. G. Harmon in the Proceedings of the PEARL Workshop uber Realzeitsysteme, December 1994, pages 68-76.

  4. "Supporting User-Friendly Analysis of Timing Constraints" by L. Ko, D. B. Whalley, M. G. Harmon in the Proceedings of the ACM SIGPLAN Workshop on Language, Compilers, and Tools for Real-Time Systems, June 1995, pages 107-115. [ vertical slides, horizontal slides]

  5. "Effective Exploitation of a Zero Overhead Loop Buffer" by G. Uh, Y. Wang, D. Whalley, S. Jinturkar, C. Burns, and V. Cao in the Proceedings of the ACM SIGPLAN Workshop on Language, Compilers, and Tools for Embedded Systems, May 1999, pages 10-19.

  6. "Automatic Validation of Code-Improving Transformations" by R. van Engelen, D. Whalley, and X. Yuan in the Proceedings of the ACM SIGPLAN Workshop on Language, Compilers, and Tools for Embedded Systems, June 2000.

  7. "Parametric Timing Analysis" by E. Vivancos, C. Healy, F. Mueller, and D. Whalley in the Proceedings of the ACM SIGPLAN Workshop on Language, Compilers, and Tools for Embedded Systems, June 2001, pages 88-93.

  8. "Industrial Requirements for WCET Tools - Answers to the Artist Questionnaire" by R. Wilhelm, J. Engblom, S. Thesing, and D. Whalley in the Proceedings of the EUROMICRO Workshop on WCET, June 2003, 25-29.

  9. "Enhancing the Effectiveness of Utilizing an Instruction Register File" by D. Whalley and G. Tyson in the Proceedings of the NSF PI Workshop, April 2008.

  10. "Program Differentiation" by D. Chang, S. Hines, P. West, G. Tyson, and D. Whalley in the Proceedings of the ACM Workshop on Interaction between Compilers and Computer Architecture (INTERACT), March 2010.

  11. "THIC and OpenSPARC: Reducing Instruction Fetch Power in a Multithreading Processor" by P. Gavin, S. Hines, G. Tyson, and D. Whalley in the Proceedings of the Workshop on Optimizations for DSP and Embedded Systems (ODES), April 2010, pages 34-42.

  12. "Re-Defining the Tournament Predictor for Embedded Systems" by Y. Peress, G. Tyson, and D. Whalley in the Proceedings of the Workshop on Optimizations for DSP and Embedded Systems (ODES), April 2010, pages 53-61.

  13. "Improving Low Power Processor Efficiency with Static Pipelining" by I. Finlayson, G. Uh, D. Whalley, and G. Tyson in the Proceedings of the Workshop on Interaction between Compilers and Computer Architecture (INTERACT), February 2011.

  14. "Towards a Performance and Energy-Efficient Data Filter Cache" by A. Bardizbanyan, M. Sjalander, D. Whalley, and P. Larsson-Edefors in the Proceedings of the ACM Workshop on Optimizations for DSPs and Embedded Systems (ODES), February 2013, pages 21-28.

Other Publications

  1. "A General Approach for Tight Timing Predictions of Non-Rectangular Loops" by C. Healy, R. van Engelen and D. Whalley in the WIP Proceedings of the IEEE Real-Time Technology and Applications Symposium, June 1999, pages 11-14. [ vertical slides, horizontal slides] (This was a Work in Progress (WIP) paper.)

  2. "Exploitation of a Large Data Register File" by M. Searles, D. Whalley, and G. Tyson in the Proceedings of the ACM SIGPLAN/SIGBED poster abstracts for the Conference on Language, Compilers, and Tools for Embedded Systems, June 2006, pages 37-40.

  3. "Application Configurable Processors" by C. Zimmer, G. Tyson, and D. Whalley in the Proceedings of the ACM SIGPLAN/SIGBED poster abstracts for the Conference on Language, Compilers, and Tools for Embedded Systems, June 2006, pages 49-52.

Dissertations

  1. "Ease: An Environment for Architecture Study and Experimentation" by D. B. Whalley, Dissertation (Advisor: Jack Davidson), University of Virginia, May 1990.

  2. "Static Cache Simulation and Its Applications" by F. Mueller, Dissertation (Advisor: David Whalley), Florida State University, August 1994.

  3. "Bounding Worst-Case Data Cache Performance" by R. White, Dissertation (Advisor: David Whalley), Florida State University, May 1997.

  4. "Effectively Exploiting Indirect Jumps" by G. Uh, Dissertation (Advisor: David Whalley), Florida State University, December 1997.

  5. "Automatic Utilization of Constraints for Timing Analysis" by C. Healy, Dissertation (Advisor: David Whalley), Florida State University, August 1999.

  6. "Automated Empirical Optimization of High Performance Floating Point Kernels" by R. Whaley, Dissertation (Advisor: David Whalley), Florida State University, December 2004.

  7. "Reducing the Cost of Comparisons within Conditional Transfers of Control" by W. Kreahling, Dissertation (Advisor: David Whalley), Florida State University, August 2005.

  8. "Reducing the WCET of Applications on Low End Embedded Systems" by W. Zhao, Dissertation (Advisor: David Whalley), Florida State University, August 2005.

  9. "Fast and Effective Solutions to the Phase Ordering Problem" by P. Kulkarni, Dissertation (Advisor: David Whalley), Florida State University, August 2007.

  10. "Improving Processor Efficiency through Enhanced Instruction Fetch" by S. Hines, Dissertation (Advisors: David Whalley and Gary Tyson), Florida State University, August 2008.

  11. "Improving Processor Efficiency by Statically Pipelining Instructions" by I. Finlayson, Dissertation (Advisors: David Whalley and Gary Tyson), Florida State University, August 2012.

  12. "A Presentation and Low-Level Energy Usage Analysis of Two Low-Power Architectural Techniques" by P. Gavin, Dissertation (Advisors: David Whalley and Gary Tyson), Florida State University, Spring 2015.

MS Theses (incomplete list)

  1. "Avoiding Unconditional Jumps by Code Replication" by F. Mueller, MS Thesis (Advisor: David Whalley), Florida State University, April 1991.

  2. "Fast Context Switches" by J. Snyder, MS Thesis (Advisor: David Whalley), Florida State University, April 1992.

  3. "Combining the Advantages of Direct-Mapped and Set-Associative Instruction Caches" by D. Warner, MS Thesis (Advisor: David Whalley), Florida State University, December 1992.

  4. "Graphical Visualization of Compiler Optimizations" by M. Boyd, MS Thesis (Advisor: David Whalley), Florida State University, August 1993.

  5. "Predicting Pipeline and Instruction Cache Performance" by C. Healy, MS Thesis (Advisor: David Whalley), Florida State University, December 1995.

  6. "Bounding Instruction Cache Performance" by R. Arnold, MS Thesis (Advisor: David Whalley), Florida State University, December 1996.

  7. "Decreasing Process Memory Requirements by Overlapping Run-time Stack Data" by E. Ratliff, MS Thesis (Advisor: David Whalley), Florida State University, April 1997.

  8. "Avoiding Conditional Branches by Code Replication and Interprocedural Analysis" by P. Zhang, MS Thesis (Advisor: David Whalley), Florida State University, August 1997.

  9. "Decreasing Process Memory Requirements by Overlapping Instructions" by R. Bowman, MS Thesis (Advisor: David Whalley), Florida State University, August 1997.

  10. "Improving Performance by Branch Reordering" by M. Yang, MS Thesis (Advisor: David Whalley), Florida State University, August 1998.

  11. "Using a Swap Instruction to Coalesce Loads and Stores" by A. Qasem, MS Thesis (Advisor: David Whalley), Florida State University, April 2001.

  12. "Compiler Modifications to Support Interactive Compilation" by B. Cai, MS Thesis (Advisor: David Whalley), Florida State University, April 2001.

  13. "VISTA: Vpo Interactive System for Tuning Applications" by W. Zhao, MS Thesis (Advisor: David Whalley), Florida State University, August 2001 (hardcopy is available upon request).

  14. "Performance Driven Optimization Tuning in VISTA" by P. Kulkarni, MS Thesis (Advisor: David Whalley), Florida State University, August 2003.

  15. "Using De-Optimization to Re-Optimize Code" by S. Hines, MS Thesis (Advisor: David Whalley), Florida State University, August 2004.

  16. "Effective Exploitation of a Large Data Register File" by M. Searles, MS Thesis (Advisors: David Whalley and Gary Tyson), Florida State University, December 2006.

  17. "Application Reconfigurable Processors" by C. Zimmer, MS Thesis (Advisors: Gary Tyson and David Whalley), Florida State University, December 2006.

  18. "Graphical Visualization of Architectural Simulators" by K. Jones, MS Thesis (Advisors: Gary Tyson and David Whalley), Florida State University, April 2007.

  19. "The Tagless Access Buffer: Improving Data Access Efficiency with Minimal ISA Changes" by C. Sanchez, MS Thesis (Advisor: David Whalley), Florida State University, December 2015.

  20. "Optimizing Transfers of Control in the Static Pipeline Architecture" by R. Baird, MS Thesis (Advisor: David Whalley), Florida State University, August 2016.

  21. "Dependency Collapsing in Instruction-Level Parallel Architectures" by V. Brunell, MS Thesis (Advisor: David Whalley), Florida State University, August 2017.

MS Projects (incomplete list)

  1. "Reducing Timing Analysis Complexity by Partitioning Control Flow" by N. Yaqoubi, MS Project (Advisor: David Whalley), Florida State University, August 1997.

  2. "Interprocedural Optimizations for Embedded Systems" by Y. Wang, MS Project (Advisor: David Whalley), Florida State University, April 1999.

  3. "Graduate Student Database" by N. Wallen, MS Project (Advisor: David Whalley), Florida State University, December 2008.